Qdi Kinetiz 7e Manual Transfer

• Item Checklist This item checklist is only available for retail market. Completely check your package,If you discover dam- aged or missing items, contact your retailer.

User manual QDI KINETIZ 7. Manual abstract: We provide the following solution which protects the system BIOS from being attacked by such viruses. There are two choices which can implement this function. Set the jumper (JAV) as closed, the BIOS can not be overwritten. Set the jumper (JAV) as open, meanwhile set. Download and update your QDI K7V8363 KinetiZ 7T 7B 7E motherboard BIOS - 6A6LMQ11 to the latest version.

P4I848P series mainboard QDI Utility CD 1HD ribbon cable 1 FDD cable User’s manual I/O shield. • Residential, commercial and light industry EN 50082-1 Generic immunity standard Part 1: Residential, commercial and light industry European Representative: QDI COMPUTER ( UK ) LTD QDI COMPUTER ( SCANDINAVIA ) A/S QDI SYSTEM HANDEL GMBH QDI EUROPE B. QDI COMPUTER (FRANCE) SARL QDI COMPUTER HANDELS GMBH LEGEND QDI SPAIN S.L. • Declaration of conformity Trade Name: QDI Computer ( U.

Model Name: P4I848P Responsible Party: QDI Computer ( U. Address: 41456 Christy Street Fremont, CA 94538 Telephone: (510) 668-4933 Facsimile: (510) 668-4966 Equipment Classification. • Chapter 1 Introduction..1 Key Features..2 Chapter 2 Installation Instructions..5 External Connectors..6 PS/2 Keyboard /Mouse Connector.6 USB1, USB2,USB3,USB4 and LAN Connectors.6 Parallel Port, Serial Port and SPDIF Connectors.6 1394 Port..7 Line-in jack, Mic-in jack and Speaker-out jack. • Wake-up function(JUSB, JFUSB)(optional) (optional) Onboard LAN(LAN_EN)..21.

• Caution Be sure to unplug the AC power supply before adding or re- moving expansion cards, RAM or other system peripherals, other- wise your mainboard and RAM might be seriously damaged. Caution Be sure to add some Silicone Grease between the CPU and the heatsink to keep them fully contacted to meet the heat sink require- ment. • T-- This page is intentionally left blank --his.

• Chapter 1 Chapter 1 Chapter 1 Chapter 1 Introduction P4I848P series of mainboards utilize Intel 848P + ICH5 ® (ICH5R) chipset, providing a fully compatible, high perfor- mance and cost-effective ATX platform. The new integrated technologies, together with AC’97 audio(2/6-channel), 8 USB, 2 SATA, and ATA100/66/33, give customers an advanced, multimedia solution at reasonable price. • Introduction Introduction Introduction Introduction Introduction Key Features Form factor ATX form factor of 305mm x 210mm Microprocessor Supports Intel ® Pentium 4 (Hyper-Threading) socket 478 processors Supports Intel ® Pentium 4 (Northwood) socket 478 processors at 2.4/2.6/2.8/3.06/3.2GHz with 800 MHz FSB Supports Intel Pentium 4 (Northwood) socket 478 processors at 1.8/2.0/2.2/2.26/2.4/2.53/2.66 ®. • (Reference to “PC Health Status” in BIOS) Supports hot-plug Two SATA devices including SATA HDD and CDROM/DVD ROM devices Supports 150Mbps transfer rate. BIOS Licensed advanced AWARD(Phoenix) BIOS, supports flash ROM, plug and play ready Supports IDE CDROM/SCSI/USB boot up.

P4I848P P4I848P P4I848P P4I848P P4I848P. • Introduction Introduction Introduction Introduction Introduction Green function Supports ACPI (Advanced Configuration and Power Interface) and ODPM (OS Directed Power Management) Supports ACPI power status: S0 (full-on), S1 (power on suspend), S3 (suspend to RAM), S4(suspend to Disk, depends on OS) and S5 (soft-off) Main Expansion Slots and Connectors Slot/Port (Quantity) Description. • The particular state of the jumpers, connectors and ports are illustrated in the follow- ing figures. Before setting the jumpers or inserting these connectors, please pay attention to the direction. P4I848P P4I848P P4I848P P4I848P P4I848P. • Installation Instr Installation Instr Installation Instruction Installation Instr Installation Instr uction uction uction uction External Connectors PS/2 Keyboard/Mouse Connector PS/2 keyboard connector is for the usage of PS/2 keyboard.

If using a standard AT size keyboard, an adapter should be used to fit this connector. PS/2 mouse connector is for the usage of PS/2 mouse.

• If set 2-Channel Audio mode on -6A mainboard, you can connect two speakers to the Front Left&Right jack, at the same time use the Rear Left&Right jack as Line in jack, and use the Center&Woofer jack as Microphone in jack. P4I848P P4I848P P4I848P. • Installation Instr Installation Instr Installation Instruction Installation Instr Installation Instr uction uction uction uction ATX 12V Power Supply Connector & Power Switch (POWER SW) The power switch (POWER SW) should be connected to a momentary switch. When powering up your system, first turn on the mechanical switch of the power supply (if one is provided), then push once the power switch. • LED is green blink. Check License Plate Number Free more.

When the system is in S3 status, the LED is orange on. When the system is in S4, S5 status, the LED is off. ORANGE(-) GREEN(-) LED+(VCC) SPKDATA RESET POWER HDD LED(-) LED- LED+ HDD LED(+) P4I848P P4I848P P4I848P P4I848P P4I848P. • USB5,6; USB7,8 Besides USB1,2,3,4 on the back panel, P4I848P series of mainboards also have two 8-pin headers on board which may connect to front panel USB cable( optional ) to provide additional four USB ports. USB7,8 USB5,6 Infrared Header (IrDA) This connector supports wireless transmitting and receiving device. • “Power on by Ring/LAN” as Enabled in the “Power Management Setup” section of the CMOS SETUP.

Save and exit, then boot the operating system once to make sure this function takes effect. +5V standby Signal for waking up(active low) P4I848P P4I848P P4I848P P4I848P P4I848P. • Installation Instr Installation Instr Installation Instruction Installation Instr Installation Instr uction uction uction uction Audio Connectors (CD_IN, AUX_IN, MODEM) (Available on -6A mainboard) CD_IN CD Left Channel CD Right Channel AUX_IN Right Audio Channel Left Audio Channel MODEM Mono-Out (to Modem) Phone-In (from Modem) 4-pin SMBus Connector(SMBUS) This connector allows you to connect SMBus devices.

• CPU damaged, BIOS chip absent or damaged system detect CPU and initialize chipset system detect memory system initialize PCI system initialize clockgen system detect Video and invoke Video BIOS Hyper-Threading OK LED1 LED2 LED3 LED4 LED5 P4I848P P4I848P P4I848P P4I848P P4I848P. • Installation Instr Installation Instr Installation Instruction Installation Instr Installation Instr uction uction uction uction Front Audio Interface(F_Audio) The audio interface provides two kinds of audio output choices: the FrontAudio, the RearAudio.

Their priority level is as sequence. When the FrontAudio is available, the RearAudio will be cut off. • If the connector has been closed once, the system will record the status and indicate the chassis has been opened. You can monitor or check this information from some software. CHSSEC Indicate signal P4I848P P4I848P P4I848P P4I848P P4I848P. • Installation Instr Installation Instr Installation Instruction Installation Instr Installation Instr uction uction uction uction Front IEEE 1394 port(F_1394) Besides one 1394 port on the back panel, the mainboard also have one 10-pin headers on board to provide additional IEEE 1394 port.

F_1394 TPA+ TPA. • & pin3 closed for disabling. Furthermore, the item “Wake-Up From S3 by USB”in Power Management Setup should also be set correspondingly to enable or disable this function. JUSB 1 2 3 1 2 3 Enable Disable (default) JFUSB Disable Enable (default) P4I848P P4I848P P4I848P P4I848P P4I848P. • For bus ratio unlocked processor, this overclocking feature can be implemented by setting FSB as 100x4/133x4/166x4/200x4MHz, meanwhile adjusting the bus ratio (multi- plier) in “QDI Innovation features” in AWARD BIOS CMOS Setup and memorry. Warning: Be sure your selection is right.

CPU over speeding is dangerous! • DMI information impossible. Therefore, set BIOS_WP as open when changing the system hardware configuration, or the error message “Unknown Flash Type” will be dis- played on the screen, and DMI information may not be updated. P4I848P P4I848P P4I848P.

• Installation Instr Installation Instr Installation Instruction Installation Instr Installation Instr uction uction uction uction Enable keyboard password power-on function (JKB) The mainboard provides the advanced keyboard password power-on function. Before using this function, set JKB with pin1 & pin2 closed. Otherwise, set JKB with pin2 & pin3 closed for disabling. • (Unplug the AC power supply) Onboard LAN (LAN_EN) If you want to use the onboard LAN, set LAN_EN with pin1&pin2 closed, Otherwise, set LAN_EN with pin2&pin3 closed for disable this fuction. Disable onboard LAN LAN_EN Enable onboard LAN P4I848P P4I848P P4I848P P4I848P P4I848P. • T-- This page is intentionally left blank --his.

• Setup utility for users to modify the basic sys- tem configuration. The information is stored in CMOS RAM so it retains the Setup information when the power is turned off. This chapter provides you with the over- view of the BIOS Setup. P4I848P P4I848P P4I848P P4I848P P4I848P.

Create a bootable system floppy diskette by typing Format A:/s from the DOS prompt under DOS6.xx or Windows 9x environment. Copy AWDFLASH.EXE(version>=8.24q) from the directory Utility located on QDI Driver CD to your new bootable diskette.

Download the updated BIOS file from the Website (Please be sure to download the suitable BIOS file for your motherboard. • The basic CMOS settings included in “Standard CMOS Features” are Date, Time, Hard Disk Drive Types, Floppy Disk Drive Types, and VGA etc. Use the arrow keys to highlight the item, then use the or keys to select the value desired in each item.

P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description Figure-2 Standard CMOS Setup Menu For the items marked, press enter, a window will pop up as shown below. You can view detailed information or make modifications. Figure-2-1 IDE Primary Master Setup Menu Hard Disk Primary Master/Primary Slave/Secondary Master/Secondary Slave These categories identify the HDD types of 2 IDE channels installed in the computer system. • To support LBA or LARGE mode of HDDs, there must be some softwares involved which are located in Award HDD Service Routine(INT13h).It may fail to access a HDD with LBA (LARGE) mode selected if you are running under an Operating System which replaces the whole INT 13h. P4I848P P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description Video Set this field to the type of video display card installed in your system.

EGA/ VGA Enhanced Graphics Adapter / Video Graphic Array. For EGA, VGA, SEGA, SVGA or PGA monitor adapters. CGA 40 Color Graphic Adapter, powering up in 40 column mode. • Chapter 3 Chapter 3 Chapter 3 Chapter 3 Chapter 3 QDI Innovation Features Figure-3 QDI Innovation features Menu The following indicates the options for each item and describes their meaning.

Item Option Description [SpeedEasy setting] CPU Clock Ratio Min=8 Select the multiplication of processor core frequency. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description [RecoveryEasyII setting] Menu language Select English Select RecoveryEasyII Interface Menu language. Chinese Hotkey for NULL Backup/Recovery interface can not be used by Backup/Recovery Pressing Hotkey. F2~F12 Select Hotkey to enter Backup/Recovery interface during POST.

• Floppy, LS200, Hard Disk, CDROM, ZIP100, USB-FDD, Boot Other Device USB-ZIP,USB-CDROM,LAN Swap Floppy Drive Enabled If the system has two floppy drives, choose enable Disabled to assign physical drive B to logical drive Aand vice- P4I848P P4I848P P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description Boot Up Keypad is used as number keys. NumLock Status Keypad is used as arrow keys.

Gate A20 Option Normal The A20 signal is controlled by the keyboard controller. Fast The A20 signal is controlled by Port92.

• Set DRAM RAS# to CAS# delay 2 SCLKs,3 SCLKs CAS# Delay or 4 SCLKs. DRAM RAS#Precharge 2,3,4 Set DRAM RAS# precharge as 2,3 or 4. Memory Frequency Auto Set Memory Frequency DDR266 DDR320 DDR333 DDR400 P4I848P P4I848P P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description System BIOS Enabled Besides conventional memory, the system BIOS area Cacheable is also cacheable. Disabled System BIOS area is not cacheable.

Video BIOS Besides conventional memory, video BIOS area is Enabled Cacheable also cacheable. • Blank DPMS V-SYNC & H - SYNC signals from VGA card to monitor. This function is enabled only for VGA cards supporting DPMS. Note: When the green monitor does not detect the V/H-SYNC signals, the electron gun will be turned off.

P4I848P P4I848P P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description Video Off In The system will disable video when entering suspend Suspend mode. Do not turn off video when entering suspend mode. Suspend Type Stop Grant Select the Suspend type. PwrOn Suspend MODEM Use 3,4,5,7,9,10,11 Special Wake-up event for Modem. • Reload global timer, when there’s a FDD/COM/LPT event.

Port Disabled Do not reload global timer. PCI PIRQ[A - D] # Enabled Reload global timer, when there’s a PCI event. Disabled Do not reload global timer. P4I848P P4I848P P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description PNP/PCI Configurations Setup Figure-7 PNP/PCI Configurations Setup Menu The following indicates the options for each item and describes their meaning. Item Option Description Reset Configuration Enabled The system BIOS will reset configuration data once Data then automatically set this item as disabled.

• Secondary PCI IDE Disabled On-Chip Primary/Secondary PCI IDE is disabled. Mode 0 - 4 Define the IDE primary/secondary master/slave PIO Primary/ Secondary mode. Master/Slave PIO Auto The IDE PIO mode is defined by auto -detection. P4I848P P4I848P P4I848P P4I848P P4I848P. • BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description Disable this function. USB/USB2.0 Enabled Enable onchip USB controller. Controller Disabled Disable onchip USB controller.

USB Keyboard/ Enabled Support USB Keyboard under legacy OS. Mouse Support Disabled Do not support USB Keyboard under legacy OS. AC97 Audio Auto If audio codec was installed on board, the AC97 Audio.

• Parallel Port Mode SPP Define the parallel port mode. ECP+EPP Normal EPP Mode Select EPP1.7 Set EPP Mode as EPP 1.7 or EPP1.9 Version. EPP1.9 ECP Mode Use Set ECP Mode Use DMA 1 or 3. P4I848P P4I848P P4I848P P4I848P P4I848P.

• BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description PWRON After OFF,ON The system remains OFF/ON/Former state when the AC PWR-Fail Former-Sts power supply resumes. • C/176 F, 85 C/185 F,90 C/194 F, 95 C/145 C/151 C/158 C/167 C/176 C/185 C/194 C/205 Disabled No alarm beep. Current System The temperature inside the chassis. Current CPU The temperature of CPU. Temperature P4I848P P4I848P P4I848P P4I848P P4I848P.

• BIOS Description BIOS Description BIOS Description BIOS Description BIOS Description Current PWRFAN RPM (Revolution Per Minute) Speed of fan which is Speed connected to the fan header, CPUFAN or PWRFAN. Current CPUFAN Fan speed value is based on an assumption that Speed tachometer signal is two pulses per revolution. • If you have made all the changes to CMOS values and the system can not boot with the CMOS values selected in setup, clear CMOS after power-down, then power on again.

System will boot with BIOS default settings. P4I848P P4I848P P4I848P. • QDI Utility CD A QDI Utility CD is supplied with this mainboard, the contents contained in it are showed as below: 1. Driver Install Using this choice, you can install all the drivers for your mainboard.

You should install the drivers in order, and you need to restart your computer until all the drivers are installed. • LogoEasy II Thank you for using QDI upgraded innovation--- LogoEasy II, which is completely compat- ible with LOGOEASY. LOGOEASY II can be easily operated in a Windows environment, following in steps with the trend. It has added the functions of supporting JPEG images and true color display of 64K and 16M colors with regard to JPEG-format graphics files and the high-precision display equipment, which are now widely used. • Appendix A.

Using CBLOGO.EXE Utility (Under DOS ): 1. Copy “CBLOGO.EXE”and “AWDFLASH.EXE” from the directory Utility located on QDI Driver CD to your hard disk. Get the BIOS file from “AWDFLASH.EXE” or Download the BIOS file from the Website (and copy the BIOS file(xxxxxx.bin) to your hard disk. • (1) Multiform partition format can be supported in RecoveryEasy II, including FAT16, FAT32, NTFS etc. (2) The capability of supportable Hard Disk is up to 137GB. Flexible Combination The hard disk data can be choosed to be protected and restored as required. P4I848P P4I848P P4I848P P4I848P P4I848P.

• Please press “DEL” key to enter CMOS setup during the POST(Power On Self Test), then user can see [RecoveryEasyII Setting] items of the “QDI Innovation features” menu, in which the language on RecoveryEasyII interface and hotkey could be selected. • Press ENTER to confirm. 1 Backup Partition Table 2 Backup System Partition C: 3 Backup Whole Disk 4 Backup CMOS Setup 5 Free Backup Area 6 Exit Backup Menu figure-3 Backup Interface P4I848P P4I848P P4I848P P4I848P P4I848P. • Appendix Appendix Appendix Appendix Appendix 1 Backup Partition Table 2 Backup System Partition It is used to backup the system partition of current hard disk. It makes a backup of the data in the bootable par- tition (actived partition) of current hard disk, as well as the partition table. • Hard Disk will be overwritten. 4.Recover CMOS Setup This will restore the latest backup of the CMOS Set- tings you have made to the current CMOS.

Figure-4 Recover process P4I848P P4I848P P4I848P P4I848P P4I848P. Save and exit BIOS Setup, your system will now boot successfully. CPU SpeedEasy Setup Menu Select item from the main menu and enter the sub-menu: QDI Innovation features Menu BIOS provides you with a set of basic values for your processor selection instead of the jumper settings. BootEasy is quite easy to use, choose the right option in CMOS SETUP, ( refer to QDI Innovation features) it can be easily booted quickly. Anne Friedberg The Virtual Window Pdf.

BootEasy save all the information when PC first normally boot-up, and it restores all the pa- rameters for the system and thus let the PC boot freely and rapidly. • Appendix Appendix Appendix Appendix Appendix Using 4/6-Channel Audio The motherboard is equipped with Realtek ALC655 chip, which provides support for 6-channel audio output, including 2 Front, 2 Rear, 1 Center and 1 Subwoofer channel. ALC655 allows the board to attach 4 or 6 speakers for better surround sound effect. The section will tell you how to install and use 4/6-channel audio function on the board.

• Selecting 4- or 6-Channel Setting later in the section. Make sure all speakers are connected to Line Out connectors. Diverse connector configura- tions for 2-, 4- and 6-channel using back panel connectors are described below: P4I848P P4I848P P4I848P. • Appendix Appendix Appendix Appendix Appendix Description: Line Out, Line In and MIC functions all exist under 2-channel configuration. Description: Line In is converted to Line Out function under 4-channel configuration. • 6-Channel Analog Audio Output Description: Both Line In and MIC are converted to Line Out function under 6-channel configuration. P4I848P P4I848P P4I848P P4I848P P4I848P.

• Appendix Appendix Appendix Appendix Appendix Selecting 4- or 6-Channel Setting 1. Click the audio icon from the window tray at the bottom of the screen.

Select any surround sound effect you prefer from the “Environment” pull-down menu under the Sound Effect tab. • Testing Each Speaker 1. Click the audio icon from the window tray at the bottom of the screen. Click the Speaker Test tab. P4I848P P4I848P P4I848P P4I848P P4I848P.

• Appendix Appendix Appendix Appendix Appendix The following window appears. Select the speaker which you want to test by clicking on it. Playing KaraOK The KaraOK function will automatically remove human voice (lyrics) and leave melody for you to sing the song.

The function is applied only for 2-channel audio operation, so make sure “2 channels mode”. Select Voice Cancellation in the “Karaoke” column. P4I848P P4I848P P4I848P P4I848P P4I848P.

• Appendix Appendix Appendix Appendix Appendix CPU Installation Procedures 1. Pull the lever sideways away from the socket. Then, raise the lever up to a 90-degree angle. Look for the cut edge. The cut edge should point towards the lever pivot. The CPU will only fit in the correct orientation. • Mainboard Layout P4I848P Note: The layout includes all options.

It is for your reference only. • Top:PS/2 Mouse Bttm:PS/2 Keyboard SPDIF UART 1 Top:Line in Top:LAN(optional) Middle:Speaker out Bttm: USB3,4 Bttm:Mic. In Parallel Port Top:IEEE 1394(optional) Bttm: USB1,2 LAN_EN F_1394 ATX 12V CD_IN AUX_IN MODEM SMBUS North Bridge Socket 478 CPU_FAN South Bridge BIOS_WP DIMM1 DIMM2.

A voltage regulator coupled to the input and output terminals, wherein the voltage regulator is configured to reduce a voltage to a processor by a value dependent on a variable time allowed for the processor to transition to a reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration. CROSS-REFERENCE TO RELATED APPLICATIONS This application is a Continuation of and claims priority to U.S. Patent application Ser. 11/894,991, filed on Aug. 21, 2007, which is a Divisional of and claims priority to U.S. Patent application Ser. 09/694,433, filed on Oct.

23, 2000, which are hereby incorporated by reference in their entirety. FIELD Embodiments relate to computer systems and, more particularly, to apparatus and methods for reducing power use by a computer system during intervals in which processing is stopped. BACKGROUND As computer processors have increased in ability, the number of transistors utilized has increased almost exponentially. This increase in circuit elements has drastically increased the power requirements of such processors. As the need of power increases, the temperature at which a computer operates increases and the battery life of portable computers decreases. The loss of battery life with modern portable computers greatly reduces the time during which the computer can function as a portable device. In fact, the power usage has become so great that even with significant reduction in the process size utilized, a plethora of techniques have been implemented to reduce power usage to maintain the efficacy of portable computers.

One of these techniques monitors the use of the various devices within the computer and disables those devices that have not been utilized for some period. Because the processor utilizes a significant amount of the power (e.g., 50%) used by a portable computer, this technique is utilized to disable the processor itself when its processing requirements are unused for some interval. In the typical case, disabling the processor is accomplished by terminating the system clocks furnished to the processor.

When processor clocks have been disabled, controlling circuitry (typically a portion of the “Southbridge” circuitry of an X86-processor-based computer) remains enabled to detect interrupts requiring processor operation. The receipt of such an interrupt causes the controlling circuitry to once again enable clocks to the processor so that the processor may take whatever steps are necessary to handle the basis of the interrupt. The technique of disabling the processor reduces significantly the dissipation of power caused by the operation of the processor even at a low frequency. In fact, the technique works quite well; and it is estimated that with many portable computers the processor is placed in the state in which system clocks are disabled during approximately ninety percent of the operation of the computer.

However, use of this technique emphasizes another aspect of power loss using advanced processors. When system clocks for a processor are disabled, the processor must remain in a state (sometimes called “deep sleep”) in which it is capable of rapidly responding to interrupts. Such a state requires the application of core voltage to the various circuits. The application of this voltage generates a power dissipation referred to in this specification as “static power” usage because the processor is in its static state in which clocks are disabled. To date there has been little attention paid to this static power usage. However, the usage is very significant when a processor functions in the deep sleep mode as much as ninety percent of the time. As process technologies continue to shrink in dimension and lower operating voltages, this static power increases due to lower threshold voltages and thinner gate oxides.

It is desirable to furnish apparatus and methods for reducing the power use of a processor in the state in which its clocks are disabled. SUMMARY Embodiments are realized by a method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled. These and other features of embodiments will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views. BRIEF DESCRIPTION OF THE DRAWINGS FIG.

1 is a diagram illustrating current-voltage characteristics of CMOS transistor devices utilized in microprocessors. 2 is another diagram illustrating current-voltage characteristics of CMOS transistor devices utilized in microprocessors. 3 is a circuit diagram illustrating a first circuit designed in accordance with an embodiment for reducing static power usage.

4 is a circuit diagram illustrating a second circuit designed in accordance with an embodiment for reducing static power usage. 5 is another circuit diagram illustrating a circuit designed in accordance with an embodiment for reducing static power usage.

DETAILED DESCRIPTION FIG. 1 is a first diagram displaying a number of curves illustrating the current-voltage characteristics of CMOS transistor devices utilized in the circuits of a microprocessor. This first diagram utilizes a linear scale for both current and voltage. As may be seen, each of the curves illustrates that the drain-to-source current of a transistor is essentially nonexistent until the voltage at the gate terminal of the transistor is raised to a threshold voltage.

Once the threshold voltage of the transistor is reached, drain-to-source current increases either linearly or quadratically depending on whether the transistor is in the linear region or saturation region of operation. Although the diagram of FIG. 1 appears to illustrate that current flowing below the threshold value of the gate voltage is insignificant, this is not the case in some situations. 2 illustrates current versus voltage curves of the typical transistor device below the threshold voltage with the voltage being plotted on a log scale. As may be seen, current in fact flows below the threshold voltage.

If a transistor functions in the state below the threshold voltage for ninety percent of computer processor operation, then this current has a significant affect on power usage by the processor. Since a processor is not capable of computing in the mode in which its clocks are disabled, it would at first glance appear that the solution would be to terminate the application of voltage to the processor. However, as suggested above, it is necessary that the processor be maintained in a condition in which it can respond rapidly to interrupts provided by the circuitry that controls application of the system clocks.

To do this, the processor must maintain state sufficient to immediately return to an operating condition. Thus, prior art processors have been provided sufficient voltage to maintain such state and to keep their transistors ready to immediately respond to interrupts. In general, this has been accomplished by maintaining the processor core voltage at the same level as the operating voltage. With most prior art processors, the core voltage used by a processor is selected by use of motherboard switches or setup software at a level sufficient to provide the highest frequency operations specified for the particular processor.

For example, many processors provide 1.8 volts as a core voltage. On the other hand, the voltage required to maintain state in a deep sleep mode may be significantly less, e.g., one volt or less. Since such processors function at the same voltage whether in a computing or a deep sleep mode, a significant amount of unnecessary power may be expended. In one typical state of the art X86 processor, the power usage averages approximately one-half watt in the deep sleep state because of the leakage illustrated by the diagram of FIG. Embodiments reduce the voltage applied to the processor significantly below the lowest voltage normally furnished as a core voltage for the processor during the mode in which system clocks are disabled thereby reducing the power utilized by the processor in the deep sleep state. 3 is a circuit diagram illustrating a first embodiment.

In the circuit 10 illustrated, a switching voltage regulator 11 receives an input signal at a terminal 12 which determines its output voltage value. Most modern processors utilize a voltage regulator which is capable of furnishing a range of core voltages for operating transistors; a typical regulator may furnish a range of voltages between 2 and 0.925 volts from which a particular core voltage may be selected for operation. Typically, a binary signal is provided at the terminal 12 which selects the particular output voltage level to be furnished by the regulator 11; in such a case, a number of individual pins may be utilized as the terminal 12.

Recently, a new power saving technique has been utilized which dynamically adjusts both the voltage and operating frequency to a level sufficient to maintain computing operations being conducted by a processor. The technique which offers significant power savings is described in detail in U.S. Patent application Ser. 09/484,516, filed Jan. 18, 2000, entitled “Adaptive Power Control”, now U.S. 7,100,061, which is hereby incorporated by reference. A processor which utilizes this technique monitors operations within the processor to determine the frequency level at which the processor should operate.

Depending on the particular operations being carried out by the processor, the value furnished at the terminal 12 of a regulator functioning in such a system will cause the regulator to produce an output voltage at some level between the high and low values necessary for the particular processor to carry out computing functions. In the circuit of FIG. 3, input to the terminal 12 is furnished via a circuit 13 such as a multiplexor that is capable of providing one or more input values.

In the embodiment illustrated, a value is provided at a first input 14 to the circuit 13 by the processor (or other circuitry) which determines the operating condition of the processor in its computing range; and a second value is provided at a second input 15 which is selected especially for the deep sleep condition. Either of these input values may be selected by a control signal provided at a control terminal 16 of the circuit 13. In one embodiment, a system control signal normally utilized to signal entry into the deep sleep condition (a stop clock signal) is used as the control signal to be furnished at the control terminal 16. This control signal selects the input value furnished at the input 15 which is especially chosen to cause a typical prior art regulator 11 to produce a voltage output for operating the processor in the deep sleep mode. In one embodiment, the value furnished for deep sleep mode is chosen to cause the regulator 11 to produce the lowest voltage possible in its range of output voltages. In one exemplary processor that utilizes the technique described in the above-mentioned patent application, the processor is specified as capable of conducting computing operations in a core voltage range from a low voltage of 1.2 volts to a high voltage of 1.6 volts.

On the other hand, the processor when operating in deep sleep mode has no problem maintaining that state necessary to resume computing even though functioning at a core voltage of 0.925 volts, the lowest voltage which the regulator can provide. Thus, although the voltage regulator 11 may typically provide a range of varying output voltage levels, the lowest voltage at which a processor is specified for conducting computing operations is typically significantly above the lowest value which the regulator is capable of furnishing. In order to reduce power usage in one embodiment, in response to a control signal indicating that the processor is about to go into the deep sleep state, the value at the input 15 is furnished by the circuit 13 to the regulator causing the regulator 11 to generate its lowest possible output voltage level for the deep sleep condition. In one exemplary embodiment, the high and low voltages generated in a computing mode are 1.6 volts and 1.2 volts while the deep sleep voltage is 0.925 volts.

Although the voltage level furnished by the regulator 11 for the deep sleep mode of the processor might appear to be only slightly lower than that furnished in the lowest operating condition for the exemplary processor, the reduction in power usage is quite significant. Because both the voltage and the leakage current are reduced, the reduction in power is approximately equal to the ratio in voltage levels raised to the power of about three to four. Over any period of processor use involving the deep sleep state, such a reduction is quite large. One problem with this approach to reducing power is that it does not reduce the voltage level as far as might be possible and, thus, does not conserve as much power as could be saved. This approach only reduces the voltage level to the lowest level furnished by the regulator. This voltage is significantly greater than appears to be necessary for a processor which also dynamically regulates voltage furnished during computing operations to save power. Two criteria control the level to which the core voltage may be reduced in deep sleep.

The level must be sufficient to maintain state that the processor requires to function after returning from the deep sleep state. The level must be one that can be reached during the times allowed for transition to and from the deep sleep mode. The first criterion is met so long as values of state stored are not lost during the deep sleep mode. Tests have shown that a core voltage significantly below one-half volt allows the retention of the memory state of a processor. Thus, using this criterion, it would be desirable to reduce the core voltage to a value such as one-half volt or lower.

However, depending on system configuration, the time allowed to transition to and from deep sleep in an X86 processor can be as low as 50 microseconds. Depending on the capacitive load of the particular circuitry, a voltage variation of about 0.5 to 0.6 volts may take place during this time in one exemplary configuration. Thus, if the exemplary processor is operating at its lowest processing core voltage of 1.2 volts, its core voltage may be lowered in the time available to 0.6-0.7 volts. On the other hand, if the processor is operating at a processing core voltage of 1.5 volts, its core voltage may only be lowered in the time available to 0.9-1 volts. Consequently, it is desirable that the core voltage furnished during deep sleep be lowered to a level which may be below the level provided by a typical voltage regulator but which varies depending on the core operating voltage from which it transitions.

This desirable result may be reached utilizing a circuit such as that described in FIG. The circuit of FIG. 4 includes a feedback network 41 for controlling the level of voltage at the output of the regulator 11.

Prior art regulators such as the Maxim 1711 provide a feedback terminal and describe how that terminal may be utilized with a resistor-voltage-divider network joined between the output terminal and ground to raise the output voltage level. The embodiment illustrated in FIG. 4 utilizes the same feedback terminal and a similar resistor-voltage-divider network but joins the divider between the output terminal and a source of voltage 42 higher than the normal output voltage of the regulator to force the output voltage level to a lower value rather than a higher level. The particular source voltage and the particular resistor values may be selected to cause the voltage level at the output of the regulator to drop from a particular output value to a desired value such as 0.6 volts when transitioning from a computing level of 1.2 volts. By appropriate choice of the resistor values of the divider network 41 and the source 42, the voltage drop provided by such a divider network accomplishes the desired result of providing an output voltage for the deep sleep mode of operation that varies from the previous processor computing core voltage by an amount attainable during the transition period available. In one embodiment, resistor 43 was chosen to be 1 Kohms, resistor 45 to be 2.7 Kohms, and source 42 to be 3.3 volts. Such values cause the voltage drop into deep sleep mode to be between 0.5 and 0.6 volts whether beginning at core voltages of 1.2 or 1.6 volts.

On the other hand, by using a higher value of voltage at source 45 and adjusting the values of resistors 41 and 43, the increments of voltage drop reached from different starting voltages to final deep sleep voltage values at the terminal 12 may be brought closer to one another. It should be noted that the circuitry of FIGS. 3 and 4 may be combined so that both input selection and output adjustment are both used to adjust the core voltage value produced by a voltage regulator for deep sleep mode in particular instances where the load capacitance is relatively low. Prior art voltage regulators function in at least two different modes of operation. A first mode of operation is often referred to as “low noise” or “continuous” mode. In this mode, the regulator responds as rapidly as possible to each change in voltage thereby maintaining the output voltage at the desired output level as accurately as possible.

In order to maintain this mode of rapid response, regulators consume a certain amount of power. When a regulator is supplying a significant amount of power to the load, the power required to operate in continuous mode is relatively small. But, when a regulator is supplying a small amount of power to the load, the power used to operate the regulator in continuous mode becomes significant, and reduces the efficiency of the regulator significantly. It is common for regulators operating in the continuous mode to transfer charge from the supply capacitors back into the power source when the output voltage is changed from a higher voltage to a lower voltage. The regulator can later transfer that charge back to the regulator output capacitors.

Thus, most of the charge is not wasted. A second mode of operation by voltage regulators is often referred to as “high efficiency,” “burst,” or “skip” mode. In this mode, a regulator detects the reduction in load requirements (such as that caused by a transition into the deep sleep state) and switches to a mode whereby the regulator corrects the output voltage less frequently. When there is an increase in load requirements, the regulator switches back to the continuous mode of regulation during which more rapid correction occurs. This has the positive effect of reducing the power consumed by the regulator during deep sleep thereby increasing the regulator efficiency and saving system power. But, as a result of reducing the regulator response rate, there is more noise on the regulator output.

It is common for regulators operating in the high efficiency mode to drain the charge on the supply capacitors during a high to low voltage transition on the power supply output or to allow the load to drain the charge. Thus, the charge is wasted during high to low voltage transitions. It is typical to operate a voltage regulator in the high efficiency mode. Consequently, there is some waste of power whenever a regulated processor goes into the lower voltage deep sleep mode. If the processor is constantly being placed in deep sleep mode, then the loss of power may be quite high. Different operating systems may increase the waste of power by their operations. For example, an operating system that detects changes in operation through a polling process must constantly bring a processor out of deep sleep to determine whether a change in operating mode should be implemented.

For many such systems, such a system causes an inordinate amount of power waste if a processor would otherwise spend long periods in the deep sleep mode. On the other hand, an operating system that remains in deep sleep until an externally-generated interrupt brings it out of that state wastes power through operating the regulator in the high efficiency mode only when the processor is placed in the deep sleep state. Embodiments utilize the ability of regulators to function in both the high efficiency mode and the continuous mode to substantially reduce power wasted by transitioning between a computing and a lower voltage deep sleep mode. Although regulators have not been dynamically switched between high efficiency and continuous modes, in one embodiment, an additional controlling input 50 as shown in FIG. 5 is added to the regulator for selecting the mode of operation of the regulator based on whether the processor being regulated is transitioning between states. If the regulator receives a control signal 51 indicating that the processor is to be placed into the deep sleep mode, for example, then a regulator operating in the high efficiency mode immediately switches to the continuous mode during the voltage transition. Assuming that the regulator returns the charge to the battery during continuous mode, this has the effect of reducing the waste of power caused during the transition.

Once the transition has completed, the regulator switches back to the high efficiency state for operation during the deep sleep mode of the processor. For regulators that do not conserve capacitive charge by transferring the charge to the battery, a circuit for accomplishing this may be implemented or a capacitor storage arrangement such as a charge pump 53 for storage may be added. Alternatively, when transitioning to deep sleep, the regulator could switch to a mode where the regulator does not actively drive the voltage low but allows the capacitor charge to drain through the load.

The selection of power savings modes is dependent on the processor leakage current, the voltage drop between the operating and deep sleep voltages, and the efficiency of the regulator in transferring charge from the capacitors to the power source and then back. If the leakage current is not sufficient to bring the voltage down more than (1−efficiency)*(deep sleep voltage drop) during the deep sleep interval, then it is more advantageous to use the load to drain the charge on the capacitors. Otherwise, the charge on the capacitors should be transferred back to the power source. The control signal utilized may be the same control signal (stop clocks) that signals the transition into the deep sleep state if the method is to be used only for transitions between operating and deep sleep states. Alternatively, a control signal generated by a particular increment of desired change may be utilized for voltage changes within the computing range of the processor as well as the transition to deep sleep mode. Although the disclosure has been described in terms of embodiments, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the disclosure. The disclosure should therefore be measured in terms of the claims which follow.

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